This invention relates generally to electrically erasable programmable read-only memory (EEPROM) devices. More particularly, it relates to an EEPROM cell having an improved tunnel window which permits programming via a P+ contacted inversion layer so as to produce better programming endurance.
As is generally well-known in the art, electrically erasable programmable read-only memory devices can be both erased and programmed electrically without the necessity of exposure to ultraviolet light. Typically, an EEPROM memory cell is formed of three transistors consisting of a write or program transistor, a read transistor, and a sense transistor. Such a conventional EEPROM memory cell 10 is illustrated schematically in FIG. 1 and includes a write transistor 12 and an inverter. The inverter is formed of an NMOS read transistor 16 and a floating gate PMOS read transistor 14. The PMOS read transistor 14 and the NMOS read transistor 16 are connected so as to function as a sense inverter which creates a so-called xe2x80x9czero-power cellxe2x80x9d. The read transistor 14 has its source connected to a VD line 18 and its drain connected to the drain of the read transistor 16. The read transistor 14 has its floating gate FG capacitively coupled via a tunneling oxide diode D to the source of the write transistor 12. The substrate of the tunnel diode D is a highly-doped active area which is referred to as a program junction. The floating gate FG is also capacitively coupled to Control Gate line CG via a gate capacitor C. The write transistor 12 has its drain connected to a word bitline WBL and its gate connected to a word line WL. The read transistor 16 has its gate connected to the gate of the read transistor 14 and its source connected to a VS line 20.
The various voltages applied to the EEPROM memory cell 10 of FIG. 1 for programming and erasing operations, respectively, are listed in the Table below:
In order to program the EEPROM memory cell, an intermediate voltage Vpp (typically 11 V-12 V) is applied to the bitline WBL of the write transistor 12 and a relatively high voltage Vpp+ (typically 13 V-15V) is applied to the word line WL so as to pass the voltage Vpp to the source of the write transistor 12. It will be noted that the Control Gate line CG, VD line 18, and VS line 20 are all grounded. Under this bias condition, hot electrons are accelerated across the tunneling diode D from floating gate FG to source of the write transistor 12, creating a voltage drop therebetween. Since the electrons are tunneling from the floating gate FG, this results in the storing of a positive charge on the floating gate of the read transistor 14.
In order to erase the EEPROM memory cell, a relatively high voltage Vpp+ (typically +13 V-15 V) is applied to the Control Gate line CG and a small positive voltage Vbb (i.e., +5 V) is applied to the word line WL, the VD line 18, and the VS line 20. The bitline WBL of the write transistor 12 is grounded. Under this bias condition, electrons are drawn back through the tunneling diode D from the source of the write transistor and onto the floating gate FG, creating a voltage drop therebetween. Since the electrons are tunneling to the floating gate, this results in the storing of a negative charge on the floating gate of the read transistor 14.
As is also known in the art, the key to the programming and erasing operations for Fowler-Norheim current injection is the tunneling oxide diode D. More specifically, the important element is the portion of the tunnel oxide through which the electrons flow which is sometimes referred to as a tunneling window. During the programming process for the conventional EEPROM memory cell, the high electric fields across the tunneling oxide will cause a gate negative Fowler-Norheim current to flow so as to create a voltage drop in the depletion region of the program junction. As a consequence, there will be created charge trapping centers and band bending at the polysilicon edge which in turn degrades the programming performance.
In view of this, it would still be desirable to provide a method for fabricating a tunnel oxide window for use in an EEPROM process which eliminates the problem of a voltage drop during programming. This is achieved in the present invention by the provision of a P+ implant at the tunnel window edge which allows programming of the EEPROM memory cell through a P+ contacted inversion layer instead of the programming junction.
In accordance with a preferred embodiment of the present invention, there is provided a method for fabricating a tunnel oxide window for use in an EEPROM memory device. A PRJ region is implanted in a semiconductor substrate. A tunnel oxide layer is formed on the top surface of the PRJ region. A floating gate electrode is then formed over the tunnel oxide on the top surface of the PRJ region. A first type of impurity ions is implanted into the PRJ region on a first side of the floating gate electrode with the gate electrode acting as a mask so as to form an N-type lightly-doped drain region. A second type of impurity ions is implanted into the PRJ region on a second side of the gate electrode with the gate electrode acting as a mask so as to form a P-type lightly-doped drain region.
First and second sidewall spacers are formed on the respective first and second sides of the gate electrode. The first type of impurity ions is implanted into the PRJ region on the first side of the gate electrode with the gate electrode and the first sidewall spacer acting as a mask so as to form a highly-doped N+ diffusion region. The second type of impurity ions is implanted into the PRJ region on the second side of the gate electrode with the gate electrode and the second sidewall spacer acting as a mask so as to form a highly-doped P+ contacted inversion layer.
In another aspect of the present invention, there is provided an EEPROM memory cell which includes a PRJ region implanted in a semiconductor substrate and a tunnel oxide layer implanted on the top surface of the PRJ region. A floating gate electrode is formed over the tunnel oxide on the top surface of the PRJ region. A first type of impurity ions is implanted into the PRJ region on a first side of the gate electrode with the gate electrode acting as a mask so as to form an N-type lightly-doped drain region. A second type of impurity ions is implanted into the PRJ region on a second side of the gate electrode with the gate electrode acting as a mask so as to form a P-type lightly-doped drain region.
First and second sidewall spacers are formed on the respective first and second sides of the gate electrode. The first type of impurity ions is implanted into the PRJ region on the first side of the gate electrode with the gate electrode and the first sidewall spacer acting as a mask so as to form a highly-doped N+ diffusion region. The second type of impurity ions into the PRJ region on the second side of the gate electrode with the gate electrode and the second sidewall spacer acting as a mask so as to form a highly-doped P+ contacted inversion layer.